Applied's work with IMEC is part of IMEC's nanoelectronics research platform, which includes leading chipmaker partners Infineon, Intel, Panasonic/Matsushita, Philips Semiconductors, Samsung, STMicroelectronics, Texas Instruments and TSMC.
Dr. Luc Van den hove, vice president, Silicon Process and Device Technology of IMEC, said, "We selected Applied Materials as one of our key equipment providers for our core program on sub-45nm CMOS research, which is being carried out in cooperation with leading IC manufacturers. This critical development program will build on Applied Materials' extensive integration expertise in interconnect technology, especially in the areas of advanced low k dielectrics and copper conductors. With this new set of Applied interconnect systems we will have world-class capability for developing the sub-32nm generation back end process flow, and we expect to be collecting 32nm data from this tool set by the end of 2006."
As part of the joint program, Applied Producer CVD systems will be installed at IMEC, including tools to deposit Black Diamond II with Nanocure UV curing technology and BLOk low k films. An Applied Reflexion LK CMP system will be used for copper/low k planarization, featuring advanced process control and low downforce technology for polishing low k dielectric materials. An Applied Slimcell ECP system will be delivered to provide next-generation profile control of critical copper layers, and the Applied Endura Barrier/Seed system with the latest preclean technology will be used to deposit the critical barrier and seed layers in nanometer-scale features with superior step coverage using ALD and PVD technologies.
"This alliance between IMEC and Applied Materials enables us to utilize a broad range of our industry-leading interconnect technologies to develop highly integrated, high-performance 32nm and below manufacturing processes," said Dr. Farhad Moghadam, senior vice president and general manager of Applied Materials' Thin Films Group. "This kind of expert collaboration is essential to better understand the complex interface engineering and circuit scaling issues that our customers will face with advanced technology nodes."
Source: IMEC
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