Shanghai Research Center for Integrated Circuit Design and Cadence Introduce New CPU/DSP Core-Based Methodology for SOC

"We are pleased to cooperate with Cadence to cultivate the mainstream design industry in China through this SoC reference methodology project," said Ye Wang, vice director of ICC. "This methodology enables a proven design flow for our mutual customers to quickstart, follow-through and complete their SoC chip designs effectively. This methodology reduces the risk of design failures, ensuring predictable performance and reducing the overall development time to silicon. These elements are particularly important for China's local enterprises to grow their SoC chip business when they are young."

Based on the Cadence Encounter™ digital IC design and Incisive functional verification platforms, the reference methodology was built upon CPU and DSP cores from leading processor IP providers. The implementation flow was validated with several leading foundries on their 0.18-micron processes. The tools supported in the reference methodology include NC-Sim, Conformal®-ASIC, Nano Encounter™, CeltIC™, Fire & Ice® QXC, VoltageStorm®, SignalStorm® and CoWare ConvergenSC Advanced System Designer through a Cadence and CoWare strategic partnership.

"The ability to implement SoC design quickly and meet the market timeframe is critical for success in today's China IC markets," said Wayne Tang, president of Cadence China operations. "This reference methodology provides the right mix of technologies to address the needs of China's IC design engineers. The result of our successful collaboration with ICC is to provide a complete, one-stop CPU/-based SoC solution. It also symbolizes the Cadence commitment to the China IC industry."

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San Jose, CA , May 24, 2004

Cadence Design Systems, Inc. (NYSE:CDN) today announced the availability of a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometer process platform. The Cadence reference flow seamlessly integrates intellectual property (IP) developed by Artisan Components, Inc. for the IBM-Chartered cross-foundry design enablement program. Developed in conjunction with IBM, this RTL-to-GDSII reference flow—based on the Cadence Encounter digital IC design platform—is optimized across the front-to-back design chain. It offers chip designers a predictable path for system-on-chip (SoC) design from RTL to first-pass silicon.
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Shanghai Research Center for Integrated Circuit Design and Cadence Introduce New CPU/DSP Core-Based Methodology for SOC

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