UMC's Researchers Extend Traditional Nitrided Gate-oxide to beyond the 65nm node

Nitrogen profile engineering used to downscale effective oxide thickness towards 1nm to improve semiconductor performance

UMC, a world leading semiconductor foundry, today announced that its research and development team has achieved a significant engineering milestone by shrinking the Equivalent Oxide Thickness (EOT) of nitrogen doped silicon oxide (Oxy-nitride, SiON) gate dielectrics to approximately 1.0 nm using a new nitrogen profile engineering technique. This accomplishment allows more aggressive scaling of transistors to enhance overall semiconductor performance without the introduction of new materials.

"UMC's R&D team is continually developing new and innovative solutions to overcome ever-emerging challenges brought by advanced process technology," said S. F. Tzou, director of UMC's Advanced Module Development Division. "This latest achievement demonstrates that our nitrogen profile engineering technique can be used to improve performance at 65nm. This success also gives us confidence in the viability of extending SiON gate dielectrics for future CMOS applications beyond 65nm."

The novel SiON gate dielectric processing technique, unveiled by UMC engineers, enables the precision positioning of the nitrogen doping profile as well as accurate control of thickness. UMC engineers used a less than 3% nitrogen atomic concentration layer near the bottom Si-substrate / SiON interface, while using a higher concentration of nitrogen at the top interface of the poly silicon gate/SiON gate dielectric. The newly achieved effective oxide thickness of ~1.0 nm exhibits a gate leakage current of less than 10A/cm2 with improved PMOS threshold voltage stability, lower interface state density, and resistance to boron penetration. The enhanced mobility also signifies higher performance and process reliability at the same time.

Scaling down the conventional oxy-nitride to below 1.2nm of EOT typically results in the rapid escalation of gate leakage current. The use of a heavier nitrogen concentration, a favored method to reduce leakage, typically induces undesirable side effects such as mobility degradation and threshold voltage shift. Thus, this approach is not ideal for practical use. New high-k gate dielectric materials associated with metal gate electrodes have also been proposed to alleviate this barrier, though these inevitably come with new challenges of their own: namely, carrier mobility degradation, unacceptable threshold voltage instability, and dual work-function metal gate integration issues, etc. that would require intensive and costly research efforts to address.

Oxy-nitride, which has been used for decades in semiconductor manufacturing for legacy process technology generations, has remained a viable candidate, but only if a proven means could be implemented to suppress escalation of the gate leakage current while reducing thickness. Traditionally, increased power consumption due to leakage has been viewed as a trade-off with lower EOT to gain more speed. UMC has demonstrated through its new nitrogen profile engineering technique that existing oxy-nitride can be used to achieve greater transistor performance without having to sacrifice power consumption.

The details of this technology finding were reported in the Symposia on VLSI Technology and Circuits held at Kyoto, Japan on June16, 2005.

Related stories:

TSMC Qualifies Applied Materials' Gate Stack System for Its Leading-Edge 65nm Transistor Processes
Applied Materials, Inc. announced today that Taiwan Semiconductor Manufacturing Co. (TSMC) has qualified the Applied Centura Gate Stack system with DPN (decoupled plasma nitridation) technology for all of its 65nm-generation transistor fabrication processes. This advanced technology enabled TSMC to achieve their 65nm equivalent oxide thickness (EOT) scaling targets while increasing device speed.
Toshiba develops basic technology for world's smallest flash memory element in 10nm generation
Toshiba Corporation today announced that it has developed a new double tunneling layer technology applicable to future 10nm generation flash memories.
IMEC increases performance of high-k metal gate planar CMOS and FinFETs
At today’s IEEE International Electron Devices Meeting, IMEC reports significant progress in improving the performance of planar CMOS using hafnium-based high-k dielectrics and tantalum-carbide metal gates targeting the 32nm CMOS node.
Organic Transistors: Researchers produce high performance field-effect transistors with thin films of Carbon 60
Using room-temperature processing, researchers at the Georgia Institute of Technology have fabricated high-performance field effect transistors with thin films of Carbon 60, also known as fullerene. The ability to produce devices with such performance with an organic semiconductor represents another milestone toward practical applications for large area, low-cost electronic circuits on flexible organic substrates.
Novel gate dielectric materials: perfection is not enough
For the first time theoretical modeling has provided a glimpse into how promising dielectric materials are able to trap charges, something which may affect the performance of advanced electronic devices. This is revealed in a paper published on the 12th October in Physical Review Letters by researchers at the London Centre for Nanotechnology and SEMATECH, a company in Austin, Texas.
Sematech Reveals Details on Practical High-K Metal Gate Systems for 45nm And Beyond
Building on their successful CMOS solution for gate‑first, thermally stable, high-k dual metal gates, SEMATECH researchers have released further data that portends a new era in which future transistor scaling is dominated by heterogeneous integration of new materials onto silicon.
SEMATECH and NIST Collaborate on Chemical Analysis of Advanced Gate Dielectrics
Nitrogen incorporation in thin HfO₂/SiO₂ film systems representative of high-k gate dielectric layers in advanced metal-oxide semiconductor field-effect transistors (MOSFETs) has been investigated by synchrotron x-ray photoelectron spectroscopy to elucidate variations in chemical composition between samples annealed in NH₃ and N₂ ambient as a function of temperature. In addition, depth profiling of core-level binding energy spectra has been obtained by variable kinetic energy x-ray photoelectron spectroscopy (VKE-XPS) with tunable photon energy. An HfO₂/SiO₂ “interface effect” has been detected in the Si 1s spectra characterized by a shift of the Si₄+ feature to lower binding energy with no corresponding chemical state change observed in the Hf 4f spectra acquired over a broad range of electron take-off angles.
Scientists construct complementary circuits from organic materials
A flat screen that can be rolled up and put into a jacket pocket - organic transistors with low energy consumption could make this possible. Scientists at the Max Planck Institute for Solid State Research in Stuttgart and at the Universities of Stuttgart and Erlangen have constructed complementary circuits from organic transistors characterised by low supply voltages and low consumption values. These energy-saving electronic components consist of two different transistor types.

News discussion:

Technology news