[Home]
[Full version]
ASM, IMEC Demonstrate Tree Generations of Aurora Low-K Materials
Dec 06 ,Technology
ASM International and IMEC announce that they have demonstrated three generations of ASM’s Aurora® low-k and SiC dielectric barrier materials for IMEC’s 300mm pilot line.
These results have been established within the framework of the ASM - IMEC strategic partnership on Back-end-of-Line (BEOL) interconnect technology, which was announced on July 12, 2005. In this strategic partnership, IMEC and ASM will develop novel copper/low-k interconnects on 300mm wafers for application in chips of the nanotechnology era, with feature sizes of 45nm or less.
"The Aurora materials are known for their superior mechanical properties," comments Tominori Yoshida, ASM’s Business Unit Manager for PECVD. "Better mechanical properties, such as elastic modulus and hardness, and small pore size, usually makes materials more suitable for integration in a multi-layer interconnect and packaging", he continues. As with the first generation material, the next generations Aurora ultra low-k materials have also been demonstrated by IMEC to have excellent mechanical properties with, for example, an elastic modulus exceeding 9 GPa at a k value of 2.5, at a pore diameter less than 2nm.
These porous Extreme Low-k layers have been successfully patterned by IMEC with ArF immersion lithography into features suitable for 45nm to 32nm device interconnect wiring.
"We are pleased that we can offer our partners the low-k materials and technologies that they need, not only for our baseline interconnect process but also for advanced development for 45nm and 32nm technology. To this end, IMEC collaborates with leading equipment and materials suppliers worldwide to offer our IDM partners all possible options for future technology development" stated Luc Van den hove, IMEC’s Vice President Silicon Process and Device Technology.
As part of the continuing strategic partnership, IMEC and ASM will research multi-layer integrations of Aurora Extreme Low-k films (k<2.5) and the feasibility of even lower k-values, suitable for sub 32 nm technologies. ASM has installed two Eagle platforms in IMEC’s 300mm pilot line to provide low-k deposition capabilities for Aurora materials with k values ranging from about 3.0 to about 2.3, and SiC dielectric barrier layers with k values ranging from about 5.0 to about 3.8. This set of available materials spans multiple generations of low-k implementations down to the 22nm technology node.
Source: ASM Int.
Related stories:
IMEC obtains record conversion efficiency of 24.7% for GaAs solar cells on Ge substrate
IMEC has realized a single-junction GaAs solar cell on a Ge substrate with a record conversion efficiency of 24.7%. The efficiency was measured and confirmed by NREL (National Renewable Energy Laboratory, US). GaAs solar cells are used in satellite solar panels and earth-based solar concentrators.
Copper's not coping: new chips call on light speed
The tiny copper wires that connect different areas of an integrated circuit may soon limit microchip-processing speeds. So European researchers have developed technologies to produce and combine semiconductor microlasers with silicon wave guides for novel, power-efficient optical connections.
Remembering the future
As electronics designers cram more and more components onto each chip, current technologies for making random-access memory (RAM) are running out of room. European researchers have a strong position in a new technology known as resistive RAM (RRAM) that could soon be replacing flash RAM in USB drives and other portable gadgets.
IMEC demonstrates viability of laser anneal for the 32nm node
At today’s IEEE International Electron Devices Meeting, IMEC reports that laser anneal is a promising option for further transistor scaling to the 32nm node. By device demonstration, IMEC shows that laser anneal allows to scale junction depth without degradation of series resistance and overlap capacitance.
International Symposium Identifies Top Issues for sub-40 nm Immersion Litho
Bolstered by evidence that 193 nm immersion (193i) lithography is here to stay, semiconductor technology leaders have identified the top five critical issues for extending the breakthrough imaging process toward the 32 nm technology generation.
Applied Materials, IMEC Team to Develop Innovative 32nm, 22nm Interconnects
Applied Materials and IMEC, Europe's leading independent nanoelectronics and nanotechnology research center, announced today a significant joint effort to develop 32nm and 22nm-node copper/low k interconnect processing technologies using a suite of Applied Materials' most advanced systems. The goal of the joint program is to address critical manufacturing challenges that chipmakers may face as they transition to future device generations, helping them to bring new products to market more rapidly while minimizing risk.
IMEC launches industrial affiliation program to develop RF-CMOS for the 45nm era
As part of IMEC’s centralized research platform for sub-45nm CMOS technologies, the new IMEC industrial affiliation program (IIAP) on Analog/RF-CMOS for the 45nm era defines its goals to keep conquering the ITRS challenges. The program aims to develop process modules and device architectures to achieve RF CMOS performance at the 45nm node and to provide the necessary models for active and passive devices. The potential of the technology will be assessed through the benchmarking of circuit demonstrators.
193nm Immersion litho on track for 45nm half pitch
Demonstrating significant progress in all aspects of the technology, 193nm immersion lithography is on track for insertion into volume manufacturing, with good prospects for extendibility to subsequent generations, concluded industry experts at the 2nd International Symposium on Immersion Lithography, held from 12 to 15 September 2005.
[Home]
[Full version]