193 nm Immersion Litho Continues to Pass Industry Scrutiny, Symposium Finds

Vancouver, BC (19 August, 2004) – With no apparent obstacles to slow its progress, 193 nm immersion (193i) lithography continues to move toward manufacturing insertion in 2007 and holds promise for future extension, an international symposium concluded here recently.

The International Symposium on Immersion and 157nm Lithography, which attracted more than 250 attendees and 72 technical papers, generally concluded that initial optimism on 193 nm immersion is being supported by hard data from full-field prototype exposure tools, plus encouraging progress in defectivity, resists, lens coatings, and mask substrates. Meanwhile, Japan's Selete consortium leads development of conventional 157 nm lithography for potential use in future manufacturing.

“Rapid progress is visible on all critical issues for the technology, and substantial ground has been covered in the two years since193 nm immersion emerged as a serious lithographic option, ” said Andrew Grenville, symposium chairman and program manager for Immersion Strategy at International SEMATECH. “The major suppliers' schedules are on track for exposure tools and resist development. For the tools, all key aspects of lithographic performance have been confirmed experimentally.”

The symposium, held August 3-5, was sponsored by SEMATECH, Selete, and IMEC. Fourth in a series of advanced optical lithography gatherings, it was convened as a forum to enable semiconductor manufacturers and suppliers to build consensus on issues affecting 193 nm immersion and 157 nm lithography development. The symposium's findings, reported in more than 40 oral presentations, included the following:

- No surprises have emerged to prevent the introduction of 193i for 65 nm half-pitch in 2007, and the outlook is positive for its extension to 45 nm half-pitch and possibly below. Potential solutions for achieving the latter include hyper-numerical aperture, improved lens design, high refractive-index fluids, high-index resists and lens material, double exposure, and related infrastructure.

- Development of 193i exposure tools and resists remains on track. Equipment suppliers ASML, Nikon and Canon forecast first-generation production tools in 2005, and second-generation exposure equipment in 2006. Also, manufacturers' experiments on prototype tools confirmed key aspects of lithographic performance, including process window and critical-dimension (CD) uniformity.

- Greater availability of prototype full-field systems will enable revealing experiments on process performance and defectivity. Tool suppliers showed such data for the first time, and provided additional information from customers – including one supplier's report on 11,000 wafers drawn from 16 groups of users.

- Researchers are effectively addressing several critical issues, including defectivity (through experiments and simulation on suppliers' alpha full-field tools); process improvements for 193i resists, with and without topcoats; significant improvements on lens coatings for final optic durability; and demonstration of mask substrates consistent with polarized illumination.

- Development of 157 nm lithography continues, but at a reduced level. Selete, which currently is installing a 157 nm scanner, will lead 157 nm infrastructure development. In addition, there are global efforts toward 157 immersion, although eventual insertion of that technology remains an open question. At the symposium, excellent progress was demonstrated on a Czochralski process (CZ) growth method for calcium fluoride lenses used in 157 nm scanners.

“The industry is optimistic about 193i, and this is supported by increasing amounts of solid data,” said Grenville. “Overall, 193i is standing up to industry scrutiny.”

Source: SEMATECH

Related stories:

Researchers Build World's Smallest SRAM Memory Cell
(PhysOrg.com) -- IBM and its development partners -- AMD, Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE) -- today announced the first working static random access memory (SRAM) for the 22 nanometer technology node, the world's first reported working cell built at its 300mm research facility in Albany, NY.
IMEC reports major progress in EUV
IMEC reports functional 0.186µm2 32nm SRAM cells made with FinFETs from which the contact layer was successfully printed using ASML’s full field extreme ultraviolet (EUV) Alpha Demo Tool (ADT). Applied Materials, using its most advanced deposition systems, was key to fabricating the ultra-small circuit structures. IMEC also completed the integration and site acceptance test of the EUV ADT in its 300mm clean room.
Researchers report finer lines for microchips: Advance could lead to next-generation computer chips, solar cells
MIT researchers have achieved a significant advance in nanoscale lithographic technology, used in the manufacture of computer chips and other electronic devices, to make finer patterns of lines over larger areas than have been possible with other methods.
AMD, Partners Produce Test Chip Using EUV Lithography
AMD, working together with its research partner, IBM, announced it has produced a working test chip utilizing Extreme Ultra-Violet (EUV) lithography for the critical first layer of metal connections across the entire chip.
ASML Ships TWINSCAN XT:1900i Lithography System for Volume Production
ASML today announced that it has shipped its first TWINSCAN XT:1900i, the world’s only lithography system capable of imaging features down to 36.5 nanometers (nm) on chips manufactured in volume. Production of the XT:1900i is now ramping up fast, as multiple orders have been placed and systems will be shipped before the end of this year to many of the world’s leading device makers.
IMEC advancing state-of-the-art in FinFETs
At this week’s VLSI Symposium, IMEC presents significant progress in the manufacturability, circuit performance and reliability of FinFETs. The results advance FinFET process technology towards being a candidate for the 32nm node and beyond.
Hynix joins IMEC's (sub-)32nm CMOS research platform
Hynix Semiconductor has entered into a strategic partnership with IMEC, Europe’s leading independent nanoelectronics research center, to perform research and development for the (sub)-32nm memory process generations.
IBM Extends Moore's Law to the Third Dimension
IBM today announced a breakthrough chip-stacking technology in a manufacturing environment that paves the way for three-dimensional chips that will extend Moore’s Law beyond its expected limits. The technology – called “through-silicon vias” -- allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.

News discussion:

Technology news