Renesas, Matsushita Develop Technique for Stablizing Operation of 45nm On-Chip SRAM

Tests of experimental chip with 512-Kbit SRAMs employing this technique have confirmed stable operation over a wide temperature range (-40°C to 125°C) and a larger operating voltage range margin with respect to process variations. The experimental SRAM chip, produced using a 45nm CMOS process, incorporated two different memory cell designs, one with a cell area of both 0.327µm2 and another with a cell area of only 0.245µm² --- the world's smallest level. The smaller memory cell was achieved with a reduced processing dimension margin.

Details of this technology advance will be presented in paper 18.3 of Session 18 at the 2007 International Solid State Circuits Conference (ISSCC 2007) now being held in San Francisco. The innovation is of considerable significance because SRAM is an essential on-chip function for SoCs and MPUs used in embedded control applications. Conflicting trends see those applications becoming more sophisticated, requiring more SRAM, even as semiconductor process shrinks are making it more difficult to produce the stable SRAM operation necessary for proper device functionality. The 45nm process generation SRAM enabled by the new fabrication technique will make it possible to implement high-performance chips at low cost because it uses bulk CMOS instead of Silicon-on-Insulator (SOI) material, the more expensive alternative.

Overcoming problems caused by inevitable variations in threshold voltage

As LSI fabrication processes become finer, the increasing miniaturization causes greater variations of transistor characteristics, especially threshold voltage (Vth), which can disrupt SRAM operation. Vth variation takes two forms. Global Vth variation occurs on a chip-by-chip or wafer-by-wafer basis due to minute disparities in transistor shape, such as gate length and gate width. Thus, it shows deviations in the same direction among chips. Global Vth variation previously has been the main challenge SRAM designers have had to overcome.

By contrast, local Vth variation is caused by fluctuation of the state of impurities in semiconductors, and arises even in adjacent transistors of the same shape. Therefore, it occurs randomly and without directivity. With the progress in transistor miniaturization, the problem of local Vth variation first manifested itself in the 90nm process generation. It is a major challenge that must be surmounted for embedded SRAM implemented in the 45nm process generation.

The semiconductor industry has been actively pursuing development of techniques for achieving stable SRAM operation. However, the problem of Vth variation as it affects the 45nm process has required further technical developments. The solution for a 6-transistor type SRAM memory cell that Renesas Technology and Matsushita have developed has two elements. One is a read-assist circuit that performs automatic adjustment linked to Vth variations. The other is a write-assist circuit that uses hierarchically structured power supply wiring.

The new read-assist circuit employs the resistance of passive elements in a compensation function that has a layout resembling that of the memory cell. Since memory cell variations and resistance value fluctuations are linked, the effects of Vth variations are reduced. The compensation function adjusts voltage automatically with respect to temperature and process variations. As a result, memory cell stability has been secured in read operations under a wide range of operating conditions, even if the symmetry of memory cell electrical characteristics degrades through increases in temperature and process variations.

The new write-assist circuit adds finer power supply lines (divided into eight) to the memory cell's column-unit power supply lines in a way that the isolation needed for the write operation is performed only where necessary. Also, it implements hierarchically structured power supply wiring. This reduces power supply line capacitance in critical areas, allowing the power supply line potential to be dropped to a low potential at high speed. Measurements on the experimental chip confirm that even under worst-case conditions (-40°C, minimum operating voltage, and worst-case process conditions), the new write-assist circuit provides a major improvement in SRAM write speed compared to an SRAM design in which it isn't used.

Source: Renesas Technology

IBM Alliances Announce Advancement in High-K/Metal Gate Technology
IBM and its joint development partners -- AMD, Chartered Semiconductor Manufacturing, Freescale, Infineon, and Samsung -- announced an innovative approach to speed the implementation of a breakthrough material known as "high-k/metal gate" in next generation 32 nanometer (32nm) computer chips.
UMC, ARM Partner to Deliver Comprehensive SOI Solutions for 65nm Technology
UMC and ARM today announced that a test chip built with ARM SOI (Silicon On Insulator) libraries was taped-out successfully on UMC's 65-nanometer (nm) SOI process. The test chip consists of a set of ARM physical IP that uses a standard cell library, an I/O library and a single-port SRAM memory compiler. This tape-out at UMC represents the next step towards mainstream adoption of nanometer SOI technology for improved speed and power in complex system on chips (SOCs).
TSMC Manufactures First Functional 65nm Embedded DRAM Device
Taiwan Semiconductor Manufacturing Company, Ltd. today announced the foundry industry’s first functional 65nm embedded DRAM customer product. The product contains millions of DRAM bits and was silicon verified first time right.
AMD and IBM Detail Early Results Using Immersion and Ultra Low-K in 45nm Chips
At the International Electron Device Meeting today, IBM and AMD presented papers describing the use of immersion lithography, ultra-low-K interconnect dielectrics, and multiple enhanced transistor strain techniques for application to the 45nm microprocessor process generation. AMD and IBM expect the first 45nm products using immersion lithography and ultra-low-K interconnect dielectrics to be available in mid-2008.
UMC Produces Working 45-nanometer ICs
UMC, a leading global semiconductor foundry, today announced that it has successfully produced functional 45-nanometer SRAM chips that feature an impressive bit cell size of less than 0.25um2. The ICs, produced using UMC's independently developed logic process, used sophisticated immersion lithography for its 12 critical layers and incorporated the latest technology advancements such as ultra shallow junction, mobility enhancement techniques, and ultra low-k dielectrics (k=2.5).
Nantero Announces Routine Use of Nanotubes in Production CMOS Fabs
Nantero, Inc., a nanotechnology company using carbon nanotubes for the development of next-generation semiconductor devices, has resolved all of the major obstacles that had been preventing carbon nanotubes from being used in mass production in semiconductor fabs. Nanotubes are widely acknowledged to hold great promise for the future of semiconductors, but most experts had predicted it would take a decade or two before they would become a viable material.
NEC Electronics Introduces Industry's First Ultra-Low-Power 55-nanometer Embedded DRAM Technology
NEC Electronics today announced the industry's first 55- nanometer CMOS-compatible embedded DRAM (eDRAM) technology, UX7LSeD.
IMEC to create solutions for sub-45nm CMOS scaling
Together with its CMOS core partners, IMEC will announce several research breakthroughs on new gate-stack technologies and multiple-gate FET (MuGFET) devices at the 2005 Symposium on VLSI Technology. A combination of advances in MuGFETs and gate-stack technology paired with lithography improvements also resulted in a new record for a fully working 6-transistor SRAM cell of just 0.274µm² in area.

Renesas, Matsushita Develop Technique for Stablizing Operation of 45nm On-Chip SRAM

Related stories:

News discussion: