Hitachi, Ltd.and Renesas Technology Corp. announced that they have developed low-voltage embedded SRAM technology for SoC's (system-on-a-chip) beyond the 90-nm process node. Using new circuit techniques, the power lines of SRAM cells were placed in a "floating state" (detached from the power supply) during write operations, and 0.8V operation was confirmed. This development will help overcome the barrier to maintaining low-voltage operation which is becoming increasingly more difficult to achieve due to process scaling, and is expected to become fundamental technology for achieving both high-performance and low-power operation in SoCs embedded in information devices, which are supporting the growth of the ubiquitous society.
In SoC's, which processes multimedia files in information devices such as cellular phones, "high-speed" and "low-power" are essential features. Conventionally, high-speed performance was achieved by transistor scaling and low-power operation by supply-voltage scaling. Beyond the 90-nm process node, however, the effect of performance variations in the transistors can no longer be ignored and achieving higher performance through conventional methods is becoming difficult. This is especially so for SRAM circuits. As the amount of data that a SoC needs to process increases, SRAM capacity must also increase, and thus even a small performance variation between transistors has a large effect on performance, making it difficult to further lower the supply voltage. Thus the supply voltage for the SRAM circuit is expected to create a limit on the degree to which low-power operation can be achieved in SoC's, and the development of new low-voltage technology for SRAM in the 90nm process node and beyond, is a considered critical issue for achieving low-power SoC's.
In response to this challenge, Hitachi and Renesas Technology have developed the low-voltage and low-power technology for embedded SRAM in SoC's beyond 90-nm process node. Features of the technology are as below:
(1) Power-line floating write techniques for low-voltage operation:
The power line of SRAM for retaining data is placed in a floating state (detached from the power supply) during a write operation, creating a condition where it is easier to re-write the data in the memory cell. This enables the write operation to be conducted with low supply voltage, and at the same time lowering the operating voltage of the entire SRAM.
(2) Write replica circuit for low-power write operation:
Conventionally, during the entire time assigned to a write operation, all the write circuits are activated in order to attain good write performance. This new technique monitors the write performance using a replica circuit, and the write-circuit activating time is changed according to the write performance. This enables unnecessary power consumption to be reduced without performance degradation.
Hitachi and Renesas have fabricated prototype chips with 32-kbit SRAM module for cache memory and 512-kbit SRAM module for working memory, and evaluated its performance. Compared to the conventional SRAM modules, the supply voltage is 100-mV lowered and the SRAM modules can operate at 0.8-V supply voltage. The write replica circuit reduces its power consumption by 18%, and achieves the power performance, 0.76 µW/MHz bit.
The circuit technology developed is expected to contribute significantly to overcoming a scaling barrier to achieving low-power and low-voltage operation in embedded SRAM beyond the 90nm process node.
These results were presented at the IEEE International Solid-State Circuits Conference (ISSCC 2005), held in San Francisco, California, U.S.A., from 6th February 2005.
Related stories:
NEC Develops World's Fastest SRAM-Compatible MRAM With Operation Speed of 250MHz
NEC Corporation today announced that it has succeeded in developing a new SRAM-compatible MRAM that can operate at 250MHz, the world's fastest MRAM operation speed.
Renesas, Matsushita Develop Technique for Stablizing Operation of 45nm On-Chip SRAM
Renesas Technology and Matsushita Electric Industrial today announced the development of a technique that achieves stable operation with 45nm process generation bulk CMOS for SRAM (Static Random Access Memory) that can be embedded in SoC (system-on-a-chip) devices and microprocessors (MPUs).
Breakthrough Ultra-High-Speed Memory Technology That Solves Scaling Pace Limit in Embedded Memory Design
NEC Electronics Corporation announced that they have succeeded in developing an ultra-high-speed memory technology that solves the design scaling limit caused by noise margin degradation in ultra-high speed embedded memory. Ultra-high-speed embedded memory devices are indispensable for next-generation, large-scale integrated (LSI) devices and high-speed computer systems. This new technology enables static random access memory (SRAM) to keep a scaling pace with complementary metal-oxide-semiconductor (CMOS) logic circuits.
Renesas Technology Releases SH7206, First SuperH™ Microcomputer Incorporating New SH-2A CPU Core
Renesas Technology Corp. today announced the release of the SH7206, the first product incorporating the new SH-2A CPU core from the SuperH™ family of 32-bit RISC (reduced instruction set computer) microcomputers. The SH7206 incorporates large-capacity
RAM and cache memory and a variety of on-chip peripheral functions, such as multifunction timer units for motor control. It is suitable for applications including industrial equipment, such as AC servos and inverters, office equipment, such as video printers, and consumer
electronics products. Sample shipments will begin in September 2004 in Japan .
SST Announces Production of 64-Mbit MPF+ Flash Memory Devices
SST (Silicon Storage Technology, Inc., NASDAQ: SSTI), a leader in
flash memory technology, announced initial production and availability of its 64-Mbit Multi-Purpose Flash Plus (MPF+) product family. The 64-Mbit MPF+ SST39VF6401 and SST39VF6402 are the latest and largest densities within SST’s MPF+ family of products. Ideal for such applications as
mobile phones, set-top boxes,
PDAs and networking equipment, SST’s 64-Mbit MPF+ flash products offer several key features, including Boot-Block, Security ID, Erase Suspend and Resume, and Hardware Reset. The MPF+ product line, which has been shipping in lower densities since 4Q03, was developed using the company’s 0.18-micron, self-aligned SuperFlash technology and offers densities ranging from 16 Mbit to 64 Mbit.
Infineon Presents Cutting Edge Research Results in Non-Volatile Memory Technologies
Munich, Germany – June 22, 2004 – Infineon Technologies is leading in the development of new non-volatile memory technologies. At the 2004 Symposia on VLSI Technologies and Circuits, June 15 - 19 in Honolulu, Hawaii, Infineon Technologies presented promising results on a broad range of non-volatile technologies for future memory products. Read about:
- 110nm NROM Technology for Code and Data Flash Products
- Infineon Explores FinFET Sub-40nm Oxide-Nitride-Oxide Transistors for High-Density Flash memory in the 16Gbit Range
- FeRAM - Small and Highly Scalable 3-Dimensional FeRAM Cell with Vertical Capacitor
UMC's Embedded DRAM, URAM Proven in 65nm Customer Silicon
UMC, a leading global semiconductor foundry, today announced that it has produced functional 65nm customer products incorporating URAM, the company's patented embedded DRAM (eDRAM) technology.
IMEC reports major progress in EUV
IMEC reports functional 0.186µm2 32nm SRAM cells made with FinFETs from which the contact layer was successfully printed using ASML’s full field extreme ultraviolet (EUV) Alpha Demo Tool (ADT). Applied Materials, using its most advanced deposition systems, was key to fabricating the ultra-small circuit structures. IMEC also completed the integration and site acceptance test of the EUV ADT in its 300mm clean room.