MIT team aims to optimize chip designs

Computer chips inside high-speed communication devices have become so small that tiny variations which occur during chip fabrication can make a big difference in performance.

The variations can cause fluctuations in circuit speed and power causing the chips not to meet their original design specifications, says MIT Professor Duane Boning, whose research team is working to predict the variation in circuit performance and maximize the number of chips working within the specifications.

The researchers recently developed a model to characterize the variation in one type of chip. The model could be used to estimate the ability to manufacture a circuit early in the development stages, helping to optimize chip designs and reduce costs.

"We're getting closer and closer to some of the limits on chip size, and variations are increasing in importance," says Boning, a professor of electrical engineering and computer science (EECS) and associate head of the department. "It's becoming much more difficult to reduce variation in the manufacturing process, so we need to be able to deal with variation and compensate for it or correct it in the design."

Boning and EECS graduate student Daihyun Lim's model characterizes variation in radio frequency integrated circuits (RFICs).

RFIC chips are integral to many of today's high-speed communication and imaging devices, such as high-definition TV receivers. Shrinking the size of a chip's transistors to extremely small dimensions (65 nanometers, or billionths of a meter), improves the speed and power consumption of the RFIC chips, but the small size also makes them more sensitive to small and inevitable variations produced during manufacturing.

"The extremely high speeds of these circuits make them very sensitive to both device and interconnect parameters," said Boning, who is also affiliated with MIT's Microsystems Technology Laboratories. "The circuit may still work, but with the nanometer-scale deviations in geometry, capacitance or other material properties of the interconnect, these carefully tuned circuits don't operate together at the speed they're supposed to achieve."

Every step of chip manufacturing can be a source of variation in performance, said Lim. One source that has become more pronounced as chips have shrunk is the length of transistor channels, which are imprinted on chips using lithography.

"Lithography of very small devices has its optical limitation in terms of resolution, so the variation of transistor channel length is inevitable in nano-scale lithography," said Lim.

The researchers' model looks at how variation affects three different properties of circuits-capacitance, resistance and transistor turn-on voltage. Those variations cannot be measured directly, so Lim took an indirect approach: He measured the speed of the chip's circuits under different amounts of applied current and then used a mathematical model to estimate the electrical parameters of the circuits.

The researchers found correlations between some of the variations in each of the three properties, but not in others. For example, when capacitance was high, resistance was low. However, the transistor threshold voltage was nearly independent of the parasitic capacitance and resistance. The different degrees of correlation should be considered in the statistical simulation of the circuit performance during design for more accurate prediction of manufacturing yield, said Lim.

The researchers published their results in two papers in February and June. They also presented a paper on the modeling of variation in integrated circuits at this year's International Symposium on Quality Electronic Design.

Source: MIT

Related stories:

Autism Consortium releases data on genes involved in autism to researchers worldwide
The Autism Consortium, a group of researchers, clinicians and families dedicated to radically accelerating research and enhancing clinical care for autism, announced today that it has completed the first genome scan for Autism Spectrum Disorders (ASD) through its Autism Gene Discovery Project and has released the reference data set to a database that autism researchers around the world can use. The scan was conducted using new, high resolution technology developed by Affymetrix on genetic data from more than 3,000 children with ASD and their families.
Renesas, Matsushita Develop Technique for Stablizing Operation of 45nm On-Chip SRAM
Renesas Technology and Matsushita Electric Industrial today announced the development of a technique that achieves stable operation with 45nm process generation bulk CMOS for SRAM (Static Random Access Memory) that can be embedded in SoC (system-on-a-chip) devices and microprocessors (MPUs).
Scientists develop method to find genetic basis for plant variation
A new research approach that allowed scientists to rapidly identify the gene responsible for high sodium levels in certain naturally occurring plant populations could have applications for the study of a wide variety of other important plant properties.
IBM to Offer 'Statistical Timing' Solutions for Chip Designers
IBM today announced it would market to companies that design advanced integrated circuits a new suite of technology solutions aimed at greatly improving the performance of their chip designs.
It is a statistical timing analysis solution created from IBM's EinsTimer suite. Now, for the first time, this design solution will be offered commercially through IBM Engineering & Technology Services (E&TS).
SRAM technology with 0.8V operation voltage
Hitachi, Ltd.and Renesas Technology Corp. announced that they have developed low-voltage embedded SRAM technology for SoC's (system-on-a-chip) beyond the 90-nm process node. Using new circuit techniques, the power lines of SRAM cells were placed in a "floating state" (detached from the power supply) during write operations, and 0.8V operation was confirmed. This development will help overcome the barrier to maintaining low-voltage operation which is becoming increasingly more difficult to achieve due to process scaling, and is expected to become fundamental technology for achieving both high-performance and low-power operation in SoCs embedded in information devices, which are supporting the growth of the ubiquitous society.

IBM Introduces Advanced Design Methodology to Increase Performance and Reduce Power Consumption in Custom Chips
SAN DIEGO, CA -- Jun 9, 2004 -- IBM today introduced an industry-first timing flow created to maximize performance and minimize power consumption in next-generation custom chips.

Called 'variation-aware timing', this revolutionary methodology is expected to reduce custom chip design turnaround time by as much as 4X and help to further enable designs that are completed right the first time, meaning faster time-to-market for customers. The methodology is targeted at application specific integrated circuit (ASIC) 130nm (nanometer), 90nm and 65nm chip designs.
Surprisingly rapid changes in the Earth's core discovered
In a recent paper published in Nature Geoscience, the geophysicist Mioara MANDEA from the GFZ German Research Centre for Geosciences, Potsdam and her Danish colleague Nils OLSEN from the National Space Institute/DTU Copenhagen, have shown that motions in the fluid in the Earth’s core are changing surprisingly fast, and that this, in turn, effects the magnetic field of our Planet.
Species extinction threat underestimated due to math glitch, says study
Extinction risks for natural populations of endangered species are likely being underestimated by as much as 100-fold because of a mathematical "misdiagnosis," according to a new study led by a University of Colorado at Boulder researcher.

News discussion:

Technology news